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6es7798-0ca00-0xa0 

各種接口芯片都需要外接串行EEPROM芯片來加載配置數據．對于串行EEPROM芯片，需要根據接口芯片數據手冊中給出的生產廠家及型號選擇。這里選擇FM93LC56。PCI9054提供4個管腳與串行EEPROM相連接，他們分別是EEDI，EEDO，EESK，EECS，對應于FM93LC56的DI，DO，SkCS這四個管腳，這4對管腳直接相連就可以，另外93Lc56的VCC管腳需要接+5V電源，GND接地。因為需要對串行EEPROM進行寫操作，串行EEPROM應處于可編程而且非保護狀態，所以PE接高電平而PRE接低電平。FM93LC56的技術手冊規定兩個管腳上拉和下拉的電阻應為10K左右。

5） PCI9054與LOCAL Bus端連接

LHOLD：申請使用本地總線，輸出信號；LHOLDA：對LHOLD應答，輸入信號；ADS：新的總線訪問有效地址的開始，在總線訪問first clock設置時，輸出信號；BLAST：表示為總線訪問的last transfer，輸出信號；LW／R#：高電平表示讀操作，低電平表示寫操作，輸出信號；LA：地址線；LD：數據線；READY：表示總線上讀數據有效或寫數據完成，用以連接PCI9054等待狀態產生器，輸入信號。

3 VeHiog HDL軟件實現

FPGA內部在PCI9054本地總線LOCAL Bus基礎之上進行設計；FPGA片內RAM或FIFO可以在QUARTUSII環境下利用利用工具MegaWizard Plug_In Manager調用功能模塊生成。單雙口、存儲容量、數據總線的寬度以及同步或異步自行定制。為與MCU或DSP等處理器通信，要設計RAM訪問仲裁模塊。決定某一時刻對RAM訪問的主方；PCI9054支持單周期、突發和DMA傳輸，在FPGA內部要設計本地端總線控制模塊，實現局部總線的狀態控制，同時產生FPGA片內RAM的讀寫時序及地址信號。

6es7798-0ca00-0xa0 

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