倫茨 e82ev222_4c
本文介紹了目前使用美國PLX公司生產的協議轉換芯片PCI9054，用verilog HDL在FPGA中產生相應的控制信號．完成對數據的快速讀寫，從而實現了與PCI總線的高速數據通訊。本系統可擴展，適用于其他PCI設備系統，具有實用價值。
2 系統實現
本系統主要由PCI9054與FPGA構成，系統結構圖以及信號連接如圖1所示。可以根據實際需要，利用FPGA的可編程性，實現預定功能，如與單片機，DSP等處理器的不同速率間接高速通信等。協議轉換芯片PCI9054作用就是為本地處理器和主機之間架起一座通信的橋梁。
圖1 系統總體結構
1） PCI9054硬件實現
PCI9054是美國PCI公司生產的先進的PCI總線接口芯片，它滿足PCI V2．2協議，支持32位33MHz時鐘PCI總線，特別適用于PCI總線外設產品的開發。PCI9054局部總線有三種工作模式：M模式、C模式和J模式，可方便地與多種微處理器連接。PCI9054的工作方式可利用模式選擇引腳（MODEO，MODE 1）加以選擇。
2） PCI9054硬件連接電路（如圖2所示）：
圖2 PCI9054硬件連接電路圖
3） PCI9054與PCI插槽信號連接
PCI9054與PCI插槽間的連接信號線，這些信號線包括地址數據復用信號AD［31：0］，總線命令信號C/BE［3：0］和PCI協議控制信號PAR，FRAME#，IRDY#，TRDY#，STOP#，IDSEL，DEVSEL#等，電路連接中將彼此對應的信號線連接在一起即可。在PCI總線信號中．除了RST#。INTA#-INTD#之外，其他所有的信號都在始終上升沿被采樣。每個信號都
有相對于時鐘前沿建立和保持時間。在此期間，不允許有信號的跳動。該時間一過，信號的變化就無關緊要了。這種建立和保持時間對于不同的信號其情形是不同的。對于AD［31：0］，PAR和IDSEL來說，只有在一定的十種邊沿上才有上述時間的要求。對于LOCK#，IRDY#，TRDY#．FRAME#，DEVSEL#，STOP#，ⅢeQ#，GNT#，SERR#和PERR#這些信號在每個時鐘前沿都有建立和保持時間。對于C/BE［3：0］#在傳輸總線命令是，要在FRAME#第一次建立時對應的時鐘邊沿上遵守建立和保持時間的關系。若傳輸字節使能信號時，要在完成一個地址期或數據期之后的每一個時鐘邊沿保證相應的建立和保持時間。
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